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Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT821
FEATURES
flip-flops
* High speed parallel registers with positive edge-triggered D-type * Ideal where high speed, light loading, or increased fan-in are * Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec Std 17 * ESD protection exceeds 2000 V per MIL STD 883 Method 3015 * Power-up 3-State * Power-up Reset
DESCRIPTION
The 74ABT821 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT821 Bus interface Register is designed to eliminate the extra packages required to buffer existing registers and provide and 200 V per Machine Model required with MOS microprocessors
extra data width for wider data/address paths of buses carrying parity. The 74ABT821 is a buffered 10-bit wide version of the 74ABT374/74ABT534 functions. The 74ABT821 is a 10-bit, edge triggered register coupled to ten 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all ten 3-State buffers independent of the register operation. When OE is Low, the data in the register appears at the outputs. When OE is High, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay CP to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC Outputs disabled; VO = 0V or VCC Outputs disabled; VCC =5.5V TYPICAL 4.6 4 7 500 UNIT ns pF pF nA
ORDERING INFORMATION
PACKAGES 24-Pin Plastic DIP 24-Pin plastic SO 24-Pin Plastic SSOP Type II 24-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT821 N 74ABT821 D 74ABT821 DB 74ABT821 PW NORTH AMERICA 74ABT821 N 74ABT821 D 74ABT821 DB 74ABT821PW DH DWG NUMBER SOT222-1 SOT137-1 SOT340-1 SOT355-1
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 TOP VIEW 7 8 9 18 17 16 15 14 13 Q5 Q6 Q7 Q8 Q9 CP 24 23 22 21 20 19 VCC Q0 Q1 Q2 Q3 Q4
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 13 10 20 SYMBOL OE D0-D9 Q0-Q9 CP GND VCC FUNCTION Output enable input (active-Low) Data inputs Data outputs Clock pulse input (active rising edge) Ground (0V) Positive supply voltage
D8 10 D9 11 GND 12
SA00223
1995 Sep 06
1
853-1616 15703
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT821
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1 13 2 3 4 5 6 7 8 9 10 11 2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 13 1 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 9 10 11
EN C2
2D
1
23 22 21 20 19 18 17 16 15 14
SA00224
SA00225
FUNCTION TABLE
INPUTS OE L L L CP Dn l h X INTERNAL REGISTER L H NC OUTPUTS Q0 - Q9 L H NC Z Z Load and read register Hold Disable outputs NC= X= Z= = = No change Don't care High impedance "off" state Low to High clock transition Not a Low-to-High clock transition OPERATING MODE
H X NC H Dn Dn H = High voltage level h = High voltage level one set-up time prior to the Low-to-High clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High clock transition
LOGIC DIAGRAM
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 D9 11
D
D
D
D
D
D
D
D
D
D
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
13 CP 1 OE 23 Q0 22 Q1 21 Q2 20 Q3 19 Q4 18 Q5 17 Q6 16 Q7 15 Q8 14 Q9
SA00226
1995 Sep 06
2
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT821
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IOUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 output in Off or High state output in Low state VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 -65 to 150 UNIT V mA V mA V mA C
DC output diode current DC output voltage3
DC output current Storage temperature range
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER Min VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 4.5 0 2.0 0.8 -32 64 10 +85 LIMITS Max 5.5 VCC V V V V mA mA ns/V C UNIT
1995 Sep 06
3
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT821
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C Min VIK Input clamp voltage VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VOH High-level output voltage VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VOL VRST II IOFF IPU/IPD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current Low-level output voltage Power-up output low voltage3 Input leakage current Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = GND or 5.5V VCC = 0.0V; VO or VI 4.5V VCC = 2.0V; VO = 0.5V; VI = GND or VCC; V OE = VCC VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 2.5 3.0 2.0 Typ -0.9 2.9 3.4 2.4 0.42 0.13 0.01 5.0 5.0 5.0 -5.0 5.0 -100 0.5 25 0.5 0.5 0.55 0.55 1.0 100 50 50 -50 50 -180 250 38 250 1.5 -50 Max -1.2 2.5 3.0 2.0 0.55 0.55 1.0 100 50 50 -50 50 -180 250 38 250 1.5 Tamb = -40C to +85C Min Max -1.2 V V V V V V A A A A A A mA A mA A mA UNIT
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V " 10%, a transition time of up to 100sec is permitted.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Min fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum clock frequency Propagation delay CP to Qn Output enable time to High and Low level Output disable time from High and Low level 1 1 3 4 3 4 125 2.1 2.8 1.0 2.2 2.7 2.8 Tamb = +25oC VCC = +5.0V Typ 185 4.1 4.6 3.0 4.1 4.7 4.6 5.6 6.2 4.5 5.6 6.2 6.1 Max Tamb = -40 to +85oC VCC = +5.0V 0.5V Typ 125 2.1 2.8 1.0 2.2 2.7 2.8 6.2 6.7 5.3 6.3 6.7 6.5 Max ns ns ns ns UNIT
1995 Sep 06
4
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT821
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Min ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup time, High or Low Dn to CP Hold time, High or Low Dn to CP CP pulse width High or Low 2 2 1 2.1 2.1 1.3 1.3 2.9 3.8 Typ 0.5 0.3 0.0 -0.3 1.8 2.8 Tamb = -40 to +85oC VCC = +5.0V 0.5V Min 2.1 2.1 1.3 1.3 2.9 3.8 ns ns ns UNIT
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
1/fMAX
Dn
CP
VM tW(H) tPHL tW(L)
VM CP tPLH VM VM
Qn
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
SA00159
Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency
OE VM tPZL OE VM tPZH VM tPHZ VOH-0.3V Qn VM VM tPLZ
Qn
VM
0V
SA00066
Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level
1995 Sep 06
5
EEE E EEEEEEEEE EEE E EEEEEEEEE EEE EEEEEEE EEE
VM VM VM VM ts(H) th(H) ts(L) th(L) VM VM
SA00107
Waveform 2. Data Setup and Hold Times
VOL+0.3V 0V
SA00067
Philips Semiconductors
Product specification
10-bit D-type flip-flop; positive-edge trigger (3-State)
74ABT821
TEST CIRCUIT AND WAVEFORM
VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V)
PULSE GENERATOR
VIN D.U.T. RT
VOUT
Test Circuit for 3-State Outputs
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SA00012
1995 Sep 06
6

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